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ChipHack/EDSAC Challenge: 6-8 September 2017

To celebrate the 60th anniversary of the BCS and its founding president, Maurice Wilkes, this workshop will recreate EDSAC on an FPGA, rather than using OpenRISC. EDSAC was designed by Maurice Wilkes and was one of the very first general purpose computers.

We'll be reusing the logic of EDSAC, but with FPGA rather than valves, and attempt to interface to modern recreations of a paper tape reader, terminal printer, startup panel and air delay line (rather than the original mercury delay line).

We shall also use the MyStorm BlackIce FPGA board. Designed for use by hobbyists and supporting the YoSys open source tool chain, the initial idea for this board came from a BCS Open Source Specialist Group meeting in May 2016.


Registration is free, but you must register in advance at the event page. ChipHack is invariably heavily over-subscribed, with a waiting list, so we will not be able to accept registrations on the day.


We shall be using the main room at Hebden Bridge Town Hall.

The Town Hall
St George's Street
Hebden Bridge HX7 7BY


Equipment provided by you

You should bring a laptop. If you have a Raspberry Pi and/or an Arduino, you may find it useful to bring these along as well. All the tools for the workshop will run on the laptop.

Equipment provided by us

We will provide.

You may keep the UART at the end of the course. The Mystorm boards will be returned to the BCS for reuse on future courses. However, if you wish, you may purchase your MyStorm board at cost for £42 (inc VAT).

Other equipment

The latter part of the workshop involves trying to interface EDSAC to recreations of some of its peripherals. We'll bring some of these with us, but if you would like to try creating your own, the design details are on GitHub.

This is a work in progress, so keep checking back for updates.

Software installation

You need to install the Yosys tool chain. All software is free and open source and will run on Linux (including on Raspberry Pi), Mac or Windows.


Discuss on the ChipHack Google Group or ChipHack 2017 Slack team.



Day Time Speaker Title
Wed 6 Sep 09:00-09:05 Jeremy Bennett Welcome
09:05-09:20 Dan Gorringe Installing and using the tools
10:00-10:20 Jeremy Bennett Basic Verilog & the LED example
10:30-11:00 Coffee/tea available
11:30-11:50 Al Wood More Verilog & the UART receiver
12:30-13:30 Lunch available''
14:00-14:20 Richard Miller Interfacing to MyStorm
15:00-15:30 Coffee/tea available
16:00-16:20 Philipp Wagner Even more Verilog & the UART transmitter
18:00 Session close
19:00 Gather in the pub (TBC)
Thu 7 Sep 09:00-09:05 Kevin Murrell Welcome
09:05-09:20 Martin Campbell-Kelly The original EDSAC (part 1)
10:00-10:20 Dan Gorringe Bringing up EDSAC
10:30-11:00 Coffee/tea available
11:00-11:20 Bill Purvis The first implementation of EDSAC in Verilog
12:00-12:20 Hatim Kanchwala The structure of the GSoC EDSAC implementation
12:30-13:30 Lunch available
14:00-14:20 Peter Bennett Recreating EDSAC peripherals
15:00-15:30 Coffee/tea available
16:00-16:20 Martin Campbell-Kelly The original EDSAC (part 2)
17:00-17:20 Ken Boak Building a simple EDSAC simulator
18:00 Session close
19:00 Gather in the pub (TBC)
Fri 8 Sep09:00-09:05 Mary Bennett Welcome
09:05-09:20 Kevin Murrell The EDSAC replica project
10:00-10:20 Everyone What next for EDSAC
10:30-11:00 Coffee/tea available
11:45 Event close